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M u lti-b y te C o n fig u r a tio n R e g is te r R e a d
n S S _ C O N F IG
S C K
S D I
X
S T A R T
R /W
A 4
A 3
A 2
A 1
A 0
X
S T A R T
R /W
A 4
A 3
A 2
A 1
A 0
X
S T A R T
R /W
A 4
A 3
A 2
A 1
A 0
S T A R T
F ir s t R e g is te r A d d r e s s
S e c o n d R e g is te r A d d r e s s
T h ir d R e g is te r A d d r e s s
S D O
H i-Z
X
X
X
X
X
X
X
X
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
F ir s t R e g is te r V a lu e
S e c o n d R e g is te r V a lu e
Figure 22
Multiple configuration register reads are also possible by sending a series of register addresses into the SPI port,
as shown in Figure 22.
3.11 SPI Data FIFO Interface
When the transceiver is used in Buffered or Packet data mode, data is written to and read from the FIFO through
the SPI interface. Two interrupts, IRQ0 and IRQ1, are used to manage the transfer procedure.
When the transceiver is operating in Buffered or Packet data mode, the FIFO interface is selected when
nSS_DATA is set to 0 and nSS_CONFIG is set to 1. SPI operations with the FIFO are similar to operations with
the configuration registers with two important exceptions. First, no addresses are used with the FIFO, only data
bytes are exchanged. Second, nSS_DATA must be toggled high and back low between data bytes when writing
to the FIFO or reading from the FIFO. Toggling nSS_DATA indexes the access pointer to each byte in the FIFO in
lieu of using explicit addressing. Figure 23 shows the timing diagram for a multiple-byte write sequence to the
TRC103 during transmit, and Figure 24 shows the timing for a multi-byte read sequence.
T R C 1 0 3 D a ta W r ite to F IF O
n S S _ D A T A
S C K
S D I
X
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
X
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
F ir s t B y te W r itte n
S e c o n d B y te W r itte n
S D O
H i-Z
X
X
X
X
X
X
X
X
H i-Z
X
X
X
X
X
X
X
X
H i-Z
Figure 23
n S S _ D A T A
S C K
T R C 1 0 3 D a ta R e a d fro m
F IF O
S D I
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S D O
H i-Z
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
H i-Z
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
H i-Z
F ir s t B y te R e a d
Figure 24
S e c o n d B y te R e a d
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TRC103 - 11/29/12
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